Computer systems often include the capability of performing out-of-order execution of instructions. Instead of executing instructions sequentially, the instructions may be analyzed for data dependencies so that instructions that do not share data dependencies can be executed in parallel via a set of pipelines. The instructions are typically fetched, decoded into micro operations, and placed into a queue from which the operations are executed.
To facilitate out-of-order execution, computer systems may include a register renaming feature, whereby data (instruction operands and instruction results) are held in a set of physical registers, which are dynamically mapped to a corresponding set of architectural (logical) registers specified by the instruction set architecture (ISA) used by the system. Register renaming aims to remove false data dependencies by renaming the physical registers associated with operations that are not truly data dependent, so that falsely dependent operations can be executed in parallel.
Renaming also facilitates speculative execution, in which operations are tentatively executed and later committed depending on whether the result of a branch operation from which the speculatively executed operations depend was successfully predicted. The results of these speculatively executed operations may be placed in renamed registers until the operations are ready to be committed.
Renaming does not prevent operations from being executed. For example, move (MOV) operations, in which data is moved from a logical source register to a logical destination register, are still placed in the queue and issued to execution units for execution. Thus, conventional out-of-order execution techniques treat MOV operations as normal operations.